Functional verification is the art and science of demonstrating that an electronic design works correctly and is ready to move from the drawing board to manufacture.
Functionally verifying a complex design is a time consuming and expensive process.
The means by which a design is functionally verified is to build a TESTBENCH, a piece of software which exercises the design and determines whether the design works correctly and whether or not sufficient testing has been done.
This book demonstrates, in a high-accessible, step-by-step manner, the Advanced Verification Methodology from Mentor Graphics, a methodology for building reusable verification components and assembling them into complex testbenches.
Application of the AVM can increase verification productivity and increase confidence that a design has been successfully verified.
The AVM includes a software library that is implemented in both SystemC and SystemVerilog, the two programming languages most commonly used for building testbenches.
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